A peripheral component interconnect (PCI) bus system is known as disclosed in JP 2005-122337 A and JP 2000-259507 A, for example.
JP 2005-122337 A and JP 2000-259507 A discloses, for example, bus systems which include a plurality of devices and a bridge (a host bridge or a bus bridge) connected to a CPU, and the devices and the bridge are connected to a PCI bus.
For example, JP 2005-122337 A discloses that, when an abnormality occurs in any one of the plurality of devices, the host bridge rapidly restarts the device in the abnormal state while suppressing an influence thereof on the other normal devices as much as possible.
Meanwhile, JP 2000-259507 A discloses that a dedicated reset signal line is provided between the bus bridge and each of the plurality of devices and that the bus bridge selectively applies a reset signal to the plurality of devices.
However, both of JP 2005-122337 A and JP 2000-259507 A fail to disclose an operation performed in a case where a link between the CPU and the bridge is down according to a restart of the CPU.